A researcher claims to have discovered a novel approach that could potentially double the speed of computers without any additional hardware costs.
The method, called Simultaneous and Heterogeneous Multithreading (SHMT), was outlined in a paper co-authored by UC Riverside associate professor of electrical and computer engineering, Hung-Wei Tseng with computer science graduate student Kuan-Chieh Hsu.
The SHMT framework currently operates on an embedded system platform that simultaneously uses a multi-core ARM processor, an NVIDIA GPU, and a Tensor Processing Unit hardware accelerator. In tests, the system achieved a 1.96 times speedup and a 51% reduction in energy consumption.
Energy reduction
Tseng explained that modern computer devices increasingly integrate GPUs, hardware accelerators for AI and ML, or DSP units as essential components. However, these components process information separately, creating a bottleneck. The SHMT seeks to address this issue by allowing these components to work simultaneously, thus increasing processing efficiency.
The implications of this discovery are significant. Not only could it reduce computer hardware costs, but it could also decrease carbon emissions from energy production needed to run servers in large data processing centers. Furthermore, it could lessen the demand for water used to cool servers.
Tseng told us that the SHMT framework, if adopted by Microsoft in a future version of Windows, could provide a free performance boost for users. The energy-saving claim of the research is based on the idea that by shortening execution time, less energy is consumed, even when the same hardware is used.
However, there’s a catch (isn’t there always?). Tseng’s paper cautions that further research is needed to address questions about system implementation, hardware support, code optimization, and which applications stand to benefit the most.
Although no hardware engineering efforts are necessary, Tseng says “we definitely need reengineering on the runtime system (e.g., OS drivers) and programming languages (e.g., Tensorflow/PyTorch)” for it to work.
The paper, presented at the 56th Annual IEEE/ACM International Symposium on Microarchitecture in Toronto, Canada, was recognized by the Institute of Electrical and Electronics Engineers (IEEE), who selected it as one of 12 papers included in their “Top Picks from the Computer Architecture Conferences” issue out later this year.
